1. Field of the Invention
The present invention relates to a semiconductor device having a circuit comprising a thin film transistor (hereinafter referred to as TFT) formed over a substrate having an insulating surface and to a method of manufacturing the same. More particularly, the present invention provides a technique suitable for use in an electro-optical device, typically a liquid crystal display device having a pixel portion and a driver circuit provided in the periphery of the pixel portion over the same substrate, and electronic equipment incorporating the electro-optical device. Note that in the present specification, the semiconductor device indicates general devices that may function by use of semiconductor characteristics, and the above electro-optical device and the electronic equipment incorporating the electro-optical device are categorized as the semiconductor device.
2. Description of the Related Art
In the electro-optical device, typically an active matrix type liquid crystal display device, a technique in which a TFT is utilized for the purpose of structuring a switching element and an active circuit has been developed. A TFT uses a semiconductor film formed on a substrate such as a glass substrate by vapor phase growth as an active layer. A material such as silicon or silicon germanium having silicon as its principal constituent is suitably utilized in the semiconductor film. The semiconductor film as such can be classified into an amorphous silicon film or a crystalline silicon film, typically a polycrystalline silicon film, depending on the manufacturing method of the semiconductor film.
The TFT that uses an amorphous semiconductor (typically an amorphous silicon) film as an active layer cannot attain an electric field effect mobility of several cm2/Vsec or more because of electronic physical properties originated in the amorphous structure, or the like. Due to this, in an active matrix type liquid crystal display device, despite being available for use as the switching element (hereinafter referred to as pixel TFT) for driving the liquid crystals in the pixel portion, the TFT using the amorphous semiconductor as the active layer has been unusable in forming a driver circuit for performing image display. Accordingly, a technique in which a driver IC utilized as the driver circuit is mounted by the TAB (Tape Automated Bonding) method or the COG (Chip On Glass) method has been employed.
On the other hand, a TFT using a semiconductor film containing a crystal structure (hereinafter referred to as crystalline semiconductor film) (typically crystalline silicon or polycrystalline silicon) as the active layer is capable of attaining high electric field effect mobility, making it possible to form various functional circuits over the same glass substrate. Besides the pixel TFT, in the driver circuit, forming other circuits on the same substrate such as a shift resister circuit, a level shifter circuit, a buffer circuit, and a sampling circuit has been realized. Such circuits are formed by using a CMOS circuit as a base circuit, which comprises an n-channel TFT and a p-channel TFT. Supported by this technique in mounting these kinds of driver circuits, it has become clear that a TFT using as an active layer a crystalline semiconductor layer that is capable of forming driver circuits in addition to the pixel portion over the same substrate is suitable for promoting reduction in weight and thickness of a liquid crystal display device.
When comparing TFTs from their characteristics, the TFT that uses the crystalline semiconductor layer as the active layer is superior. However, in order to manufacture TFTs corresponding to the various circuits other than the pixel TFT, there is a problem in that the manufacturing process becomes a complicated one, thereby increasing the number of steps. This increase in number of steps is not only a factor in the increase in production costs, but apparently also is the cause in reducing yield.
The operating conditions of the pixel TFT and the TFTs of the driver circuits are not always the same. On account of this, the characteristics that are required of a TFT are quite different. The pixel TFT is formed of the n-channel TFT and drives, as a switching element, a liquid crystal by applying a voltage to the liquid crystal. The liquid crystal is driven by an alternate current, thus a method called frame inversion driving is widely adopted. In this method, for the purpose of suppressing the power consumption low, the characteristic that is demanded of the pixel TFT is to sufficiently lower an off current value (a drain current that flows during an off-operation of the TFT). On the other hand, since a high driver voltage is applied to the buffer circuit of the driver circuit and other circuits thereof, it is necessary to raise the withstand voltage of the TFT so that it will not break when a high voltage is applied. Also, in order to make the current drive ability higher, it is necessary to sufficiently secure an on current value (a drain current that flows during an on-operation of the TFT).
As a structure of the TFT to reduce the off-current value, a low concentration drain (LDD:Lightly Doped Drain) structure is known. In this structure, there is provided a region that is doped with an impurity element at a low concentration between a channel forming region and a source region or a drain region that is formed by doping an impurity element at a high concentration, and this region is called the LDD region. Further, as a means of preventing the degradation of the on current value caused by a hot carrier, a so-called GOLD (Gate-drain Overlapped LDD) structure is known in which the LDD region is arranged so as to overlap a gate electrode via a gate insulating film. With a structure as such, the high electric field in the vicinity of a drain is alleviated, thereby preventing hot carrier injection, a known effective prevention of the degradation phenomenon.
However, there is another point that must be given attention to besides the above off current value and the on current value. For example, the bias state of the pixel TFT and the TFT of the driver circuit such as the shift resist circuit or the buffer circuit is not necessarily the same. For example, in the pixel TFT, a large reverse bias (a negative voltage in an n-channel TFT) is applied to a gate, whereas the TFT of the driver circuit basically does not operate in the reverse bias state. Also, regarding the operating velocity, the pixel TFT may be {fraction (1/100)} or less than that of the TFT of the driver circuit. The GOLD structure is highly effective in preventing the deterioration of the on current value, but on the other hand, there arises a problem in that the off current value becomes higher compared with the usual structure of an LDD. Therefore, the GOLD structure is not a preferred structure for applying to the pixel TFT. Contrarily, although the usual structure of the LDD is highly effective in suppressing the off current value, it has a low effect in relaxing the electric field in the vicinity of a drain and in preventing deterioration caused by the hot carrier injection. It is thus not always preferable to form all TFTs to have the same structure in a semiconductor device that has a plurality of integrated circuits different from one another in the operation condition, as in active matrix liquid crystal display device. The problem as such becomes apparent especially as the characteristics of crystalline silicon TFTs are enhanced and more is demanded for the performance of active matrix liquid crystal display devices.
Further, in order to stabilize the operations of these circuits to be manufactured by using the n-channel TFT and the p-channel TFT, it is necessary to set values such as the threshold voltage of the TFT and the sub-threshold coefficient (S value) within a predetermined range. In order to do this, it is necessary to examine the TFTs from both the viewpoint of the structure and the viewpoint of the materials constituting the structure.
A technique of the present invention is for solving the above problems, and an object of the present invention is to improve operation characteristics and reliability of a semiconductor device by optimizing the structure of TFTs arranged in various circuits of the semiconductor device and an electro-optical device, typically an active matrix liquid crystal display device, formed by using the TFT, in accordance with the function of the respective circuits. In addition, another object of the present invention is to realize low power consumption as well as decreasing the number of steps to thereby reduce production costs and improve yield.
Reducing the number of manufacturing steps is one of means to realize the reduction of production costs and improvement in yield. Specifically, it is necessary to reduce the number of photomasks required for manufacturing a TFT. In the photolithography technique, the photomask is used for forming a resist pattern over a substrate as a mask of the etching process. Accordingly, the use of one photomask means that other processes such as the removal of resists and the cleaning and drying process are added to the processes of the film deposition and of the etching in the steps before and after the step where the photomask is used. It also means that complicated processes such as resist coating, pre-bake, exposure, development, and post-bake in the photolithography technique are performed.
Thus, while reducing the number of photomasks, appropriate structures of TFTs arranged in various circuits are formed in accordance with the respective circuits. Specifically, it is desired that in the structure of a TFT for functioning as a switching element, importance be placed on reducing the off current value rather than the operating speed. A multi-gate structure is adopted as such a structure. On the other hand, the structure of a TFT to be provided in the driver circuit in which high speed operation is required, it is desired that importance be placed on increasing the operating speed, and at the same time, on repressing degradation caused by hot carrier injection, which becomes a serious problem as the operating speed is increased. Various ideas have been added to the LDD region of the TFT to construct such a structure. In other words, the LDD region provided between the channel forming region and the drain region is characterized by having a concentration gradient in which the concentration of conductivity controlling impurity element gradually rises as it nears the drain region. This structure is remarkably effective in relaxing the electric field that will concentrate in a depletion layer in the vicinity of the drain region.
In order to form the LDD region having the concentration gradient of an impurity element as such, the present invention employs a method of doping an ionized conductivity controlling impurity element accelerated in the electric field to thereby penetrate through a gate electrode and a gate insulating film (the present invention defines the gate insulating film as the gate insulating film provided between the gate electrode and the semiconductor layer and in contact therewith and including the insulating film extending from the gate insulating film into a region in the periphery of the gate insulating film) and to be doped into a semiconductor layer. It should be noted that throughout the present specification, this doping method of impurity element is referred to as xe2x80x9cthe through doping methodxe2x80x9d for the sake of convenience. Furthermore, the shape of the gate electrode in the through doping method of the present invention is the so-called taper shape, meaning that the thickness of the gate electrode gradually increases inward from an edge portion. Performing the through doping method with the gate electrode having the taper shape makes it possible to control the concentration of the impurity element doped in the semiconductor layer by adjusting the thickness of the gate electrode. Hence, the LDD region in which the concentration of the impurity element gradually varies along the channel length direction of the TFT can be formed.
The material used for forming the gate electrode is a heat-resistant conductive material formed from an element chosen from the group consisting of tungsten (W), tantalum (Ta), and titanium (Ti), or a compound or an alloy having the above elements as a constituent. Speedy and precise etching is performed on such heat-resistant conductive materials, and to further form the edge portion into a taper shape, dry etching using high-density plasma is applied. As a means of achieving high-density plasma, an etching apparatus that utilizes a microwave or ICP (Inductively Coupled Plasma) is suitable. Particularly, the ICP etching apparatus can easily control plasma as well as deal with the operation of processing a large area surface substrate.
References to the plasma treatment method and to the plasma treatment apparatus utilizing the ICP are disclosed in Japanese Patent Application Laid-open No. Hei 9-293600. In this application, as a means for performing high precision plasma treatment, a method of forming plasma by applying high frequency electric power to a multi-spiral coil formed from 4 whirlpool shaped coil parts connected in series via an impedance matching apparatus is utilized.
The length of each of the whirlpool shaped coil parts is set to be xc2xc times that of the wavelength of the high frequency. In addition, the plasma treatment apparatus is structured such that a different high frequency electric power is also applied to a lower electrode for holding the piece to be treated to thereby add a bias voltage.
FIG. 19A schematically shows the structure of such a plasma treatment apparatus (for example, an etching apparatus) using ICP. An antenna coil 903 is arranged on a quartz substrate 905 in the upper portion of the reaction space, and the antenna coil 903 is connected to a first high frequency power source 901 through a matching box 907. The first high frequency power source 901 is set to between 6 and 60 MHz, typically 13.56 MHz. Further, a second high frequency power source 902 is connected through a matching box 912 to a lower electrode 904 that holds a substrate 906 which is the piece to be processed. The second high frequency power source 902 is set to between 100 kHz and 60 MHz (for example between 6 and 29 MHz). If a high frequency electric power is applied to the antenna coil 903, then a high frequency current J flows in the xcex8 direction in the antenna coil 903 and a magnetic field B develops in the Z direction (Equation 1). An induced electric field E develops in the xcex8 direction in accordance with Faraday""s law of electromagnetic induction (Equation 2).
xcexc0J=r∘tBxe2x80x83xe2x80x83(Equation 1)                               -                                    ∂              B                                      ∂              t                                      =                  rot          ⁢                      xe2x80x83                    ⁢          E                                    (                  Equation          ⁢                      xe2x80x83                    ⁢          2                )            
Electrons are accelerated in the xcex8 direction in the induced electric field E and collide with gas molecules, generating plasma. The direction of the induced electric field is the xcex8 direction, and therefore the probability of energy disappearing by charged particles colliding with the reaction chamber walls and the substrate is reduced. Further, there is almost no magnetic field B downstream of the antenna coil 903, and consequently a high density plasma region spread out in a sheet shape is formed. By regulating the high frequency electric power applied to the lower electrode 904, it is possible to independently control the plasma density and the bias voltage applied to the substrate 906. Further, it is also possible to vary the frequency of the applied high frequency electric power in response to the material of the piece to be processed.
In order to obtain a high density plasma with the ICP etching apparatus, it is necessary for the high frequency current J to flow with little loss, hence the inductance of the antenna coil 903 must be reduced. For this purpose, a method of partitioning the antenna coil is effective. FIG. 19B is a diagram showing such type of structure. On a quartz substrate 911, 4 whirlpool shaped coils 910 (multi-spiral coils) are arranged and connected to the first high frequency power source 908 via a matching box 909. At this point, a peak value of the voltage that is generated can be made higher by setting the length of each coil to a value that is a plus multiple of a quarter of the wavelength of the high frequency so as to generate a stationary wave in the coils.
If the etching apparuatus using the ICP to which such multi-spiral coil is applied is employed, then the etching of the heat-resistant conductive materials may be performed well. A dry etching apparatus using the multi-spiral ICP of Matsushita Electric Corp. (model E645-ICP) is employed here. Shown in FIGS. 20A and 20B are the results of examining the taper shape of the patterned edge portion of a W film, which has been formed into a given pattern on the glass substrate. Here, the angle of the taper portion is defined as the angle of the inclination portion of the taper portion and the substrate surface (level surface) (the angle indicated by xcex81 in FIG. 4). As common conditions, the electric discharge power (high frequency power to be applied to the coil, 13.56 MHz) is set to 3.2 W/cm2, the pressure is set to 1.0 Pa, and CF4 and Cl2 are used as the etching gas. FIG. 20A shows the dependency of the angle of the taper portion on the bias power (13.56 MHz) to be applied to the substrate. The flow rate of the etching gas CF4 and Cl2 are both set to 30 SCCM. It has become apparent that the angle of the taper portion can be altered between 70xc2x0 and 20xc2x0 within a range of the bias power 128 to 384 mW/cm2.
FIGS. 24A to 24C are electron microscope photographs showing the shape of the etched W film. FIGS. 24A, 24B, and 24C are photographs showing cases where a bias power applied to the substrate is 128 mW/cm2, 192 mW/cm2, and 256 mW/cm2, respectively. As is apparent from FIG. 20A, the angle of the taper portion becomes smaller as the bias power applied to the substrate becomes higher.
Further, FIG. 20B shows the results of examining the dependency of the angle of the taper portion on the flow rate ratio of the etching gas. The flow rate of CF4 is altered in a range of from 20 to 40 SCCM with the condition that the total flow rate of CF4 and Cl2 is set to 60 SCCM. The bias power at this point is set to 128 mW/cm2. Consequently, it is possible to alter the angle of the taper portion from 60xc2x0 to 80xc2x0.
As is shown here, the angle of the taper portion is greatly altered by the amount of bias power applied to the substrate. Accordingly, the angle of the taper portion can be altered to between 5xc2x0 and 45xc2x0 by further increasing the bias power, and also by changing the pressure.
The processing characteristics in the ICP etching apparatus for the heat-resistant conductive material that forms the gate electrode is shown in Table 1. Besides the W film and a Ta film, an example of a molybdenum-tungsten (Moxe2x80x94W) alloy (composition ratio is Mo:W=48:50 wt %) that is often used as the material for the gate electrode, is shown here. Table 1 shows typical values of the etching speed, the applicable etching gas, and the selective ratio of the material to a gate insulating film that is a base of the gate electrode. The gate insulating film is a silicon oxide film or a silicon oxynitride film formed by plasma CVD. The selective ratio here is defined as the ratio of the etching speed of the gate insulating film to the etching speed of each material.
The etching speed of the Ta film is between 140 and 160 nm/min, and the selective ratio is selected from between 6 and 8. This value is superior to the value of the selective ratio between 2 and 4 of the W film with the etching speed between 70 and 90 nm/min. Therefore, the Ta film is also applicable from the viewpoint of the characteristic of the workability. Although not shown in the table, the resistivity of the Ta film is between 20 and 30 xcexcxcexa9cm compared with the resistivity of the W film, which is between 10 and 16 xcexcxcexa9cm. Hence, the Ta film resistivity is relatively higher resulting in its drawback. On the other hand, the etching speed of the Mo-W alloy is slow, between 40 and 60 nm/min, and its selective ratio is between 0.1 and 2. It can be seen from the viewpoint of the characteristic of the workability that this material is not always suitable. As can be known from Table 1, the Ta film shows the best results. However, as stated above, when the resistivity is taken into consideration, then it is determined that the W film is suitable after considering all the factors.
Although an example of the W film has been shown here, a patterned edge portion can be easily processed into a taper shape by utilizing the ICP etching apparatus in regards to the above heat-resistant conductive materials. In addition, by applying such method to provide the gate electrode and then performing the through dope method makes it possible to control the concentration of the impurity element doped in the semiconductor layer through adjustment of the thickness of the gate electrode. Hence, the LDD region in which the concentration of the impurity element gradually varies along the channel length direction of the TFT can be formed.
With the employment of such means, according to one aspect of the present invention, there is provided a semiconductor device comprising a pixel TFT formed in a pixel portion and a driver circuit comprising a p-channel TFT and an n-channel TFT formed in the periphery of the pixel portion over the same substrate, characterized in that:
the n-channel TFT of the driver circuit has a gate electrode having a taper portion, a channel forming region, a first impurity region for forming an LDD region provided so as to partly overlap the gate electrode as well as in contact with the channel forming region, and a second impurity region for forming a source region or a drain region provided outside the first impurity region;
the p-channel TFT of the driver circuit has a gate electrode having a taper portion, a channel forming region, a third impurity region for forming an LDD region provided so as to overlap the gate electrode as well as in contact with the channel forming region, and a fourth impurity region for forming a source region or a drain region provided outside the third impurity region;
the pixel TFT has a gate electrode having a taper portion, a channel forming region, a first impurity region for forming an LDD region provided so as to partly overlap the gate electrode as well as in contact with the channel forming region, and a second impurity region for forming a source region or a drain region provided outside the first impurity region;
wherein a concentration of an impurity element of one conductivity in the region overlapping the gate electrode in the first impurity region and a concentration of an impurity element of opposite conductivity in the third impurity region become higher as it goes distant from the channel forming regions to which the respective impurity regions contact; and
a pixel electrode provided in the pixel portion has a light reflective surface, is formed on a second interlayer insulating film made of an organic insulating material, and is connected to the pixel TFT via an opening provided at least in a first interlayer insulating film made of an inorganic insulating material formed above the gate electrode of the pixel TFT and in the second interlayer insulating film formed in contact with the top surface of the first interlayer insulating film, or
a pixel electrode provided in the pixel portion has light transmittivity, is formed on a second interlayer insulating film made of an organic insulating material, and is connected to a conductive metallic wiring to be connected to the pixel TFT, the conductive metallic wiring is formed via an opening provided at least in a first interlayer insulating film made of an inorganic insulating material formed above the gate electrode of the pixel TFT and in the second interlayer insulating film formed in contact with the top surface of the first interlayer insulating film.
Further, according to another aspect of the present invention, there is provided a semiconductor having liquid crystal held between a pair of substrates, characterized in that:
one substrate which has a pixel TFT disposed in the pixel section and a driver circuit comprising a p-channel TFT and an n-channel TFT disposed in the periphery of the pixel section comprises:
an n-channel TFT of the driver circuit has a gate electrode having a taper portion, a channel forming region, a first impurity region for forming an LDD region provided so as to partly overlap the gate electrode as well as in contact with the channel forming region, and a second impurity region for forming a source region or a drain region provided outside the first impurity region;
a p-channel TFT of the driver circuit has a gate electrode having a taper portion, a channel forming region, a third impurity region for forming an LDD region provided so as to overlap the gate electrode as well as in contact with the channel forming region, and a fourth impurity region for forming a source region or a drain region provided outside the third impurity region;
the pixel TFT has a gate electrode having a taper portion, a channel forming region, a first impurity region for forming an LDD region provided so as to partly overlap the gate electrode as well as in contact with the channel forming region, and a second impurity region for forming a source region or a drain region provided outside the first impurity region;
a concentration of an impurity element of one conductivity in the first impurity region and a concentration of an impurity element of opposite conductivity in the portion which overlaps the gate electrode of the third impurity region become higher as it gets distant from the channel forming regions to which the respective impurity regions are adjoined;
wherein,
a pixel electrode provided in the pixel portion has a light reflective surface, is formed on a second interlayer insulating film made of an organic insulating material, and is connected to the pixel TFT via an opening provided at least in a first interlayer insulating film made of an inorganic insulating material formed above the gate electrode of the pixel TFT and in the second interlayer insulating film formed in contact with the top surface of the first interlayer insulating film; and
the one substrate is bonded to the other substrate having a transparent conductive film formed thereon via at least one column-shape spacer formed overlapping the opening provided in the first interlayer insulating film and the second interlayer insulating film, or
the pixel electrode provided in the pixel portion has light transmittivity, is formed on a second interlayer insulating film made of an organic insulating material, and is connected to a conductive metallic wiring to be connected to the pixel TFT, the conductive metallic wiring is formed via an opening provided at least in a first interlayer insulating film made of an inorganic insulating material formed above the gate electrode of the pixel TFT and in the second interlayer insulating film formed in contact with the top surface of the first interlayer insulating film; and
the one substrate is bonded to the other substrate having a transparent conductive film formed thereon via at least one column-shape spacer formed overlapping the opening provided in the first interlayer insulating film and the second interlayer insulating film. The angle of the taper portion of the gate electrode is set between 5xc2x0 and 45xc2x0.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a pixel TFT formed in a pixel portion and a driver circuit, having a p-channel TFT and a n-channel TFT, formed in the periphery of the pixel portion on the same substrate, the method is characterized by comprising:
a first step of forming a semiconductor layer containing a crystal structure over the substrate;
a second step of forming a plurality of island semiconductor layers by selectively etching the semiconductor layer containing a crystal structure;
a third step of forming a gate insulating film in contact with the island semiconductor layers;
a fourth step of forming a conductive layer made of a heat-resistant conductive material over the gate insulating film;
a fifth step of forming a gate electrode having a taper portion by selectively etching the conductive layer;
a sixth step of forming a first impurity regions having a concentration gradient of an impurity element that imparts n-type conductivity in a direction parallel to the substrate by doping the impurity element that imparts n-type conductivity at least into the island semiconductor layers that form the n-channel TFT of the driver circuit and the pixel TFT, through the taper portion of the gate electrode and through the gate insulating film;
a seventh step of forming a second impurity regions by doping an impurity element that imparts n-type conductivity into the island semiconductor layers that form the n-channel TFT of the driver circuit and the pixel TFT, by forming a mask over the gate electrode and over the region adjacent to the gate electrode;
an eighth step of forming third impurity regions having a concentration gradient of an impurity element that imparts p-type conductivity in a direction parallel to the substrate by doping the impurity element that imparts p-type conductivity into the island semiconductor layer that forms the p-channel TFT of the driver circuit through the taper portion of the gate electrode and through the gate insulating film, and of forming at the same time a fourth impurity region by doping an impurity element that imparts p-type conductivity, but not via the taper portion of the gate electrode;
a ninth step of forming a first interlayer insulating film made of an inorganic insulating material above the n-channel TFT and the p-channel TFT of the driver circuit, and the pixel TFT;
a tenth step of forming a second interlayer insulating film made of an organic insulating material in contact with the first interlayer insulating film; and
an eleventh step of forming a pixel electrode having a light reflective surface to be connected to the pixel TFT, on the second interlayer insulating film. Or a step of forming the pixel electrode with a transparent conductive film and connecting it to the conductive metallic wiring that is to be connected to the pixel TFT may be applied.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device having liquid crystal held between a pair of substrates, said method characterized by comprising:
a first step of forming, on one substrate, a semiconductor layer containing a crystal structure, the one substrate having a pixel TFT formed in a pixel portion and a driver circuit having an n-channel TFT and a p-channel TFT formed in the periphery of the pixel portion;
a second step of forming a plurality of island semiconductor layers by selectively etching the semiconductor layer containing a crystal structure;
a third step of forming a gate insulating film in contact with the island semiconductor layers;
a fourth step of forming a conductive layer made of a heat-resistant conductive material over the gate insulating film;
a fifth step of forming gate electrodes having a taper portion by selectively etching the conductive layer;
a sixth step of forming first impurity regions having a concentration gradient of an impurity element that imparts n-type conductivity in a direction parallel to the substrate by doping the impurity element that imparts n-type conductivity at least into the island semiconductor layers that form the n-channel TFT of the driver circuit and the pixel TFT, through the taper portion of the gate electrode and through the gate insulating film;
a seventh step of forming a second impurity region by doping an impurity element that imparts n-type conductivity into the island semiconductor layer that forms the n-channel TFT of the driver circuit and the pixel TFT, by forming a mask over the gate electrode and over the region which is adjacent to the gate electrode;
an eighth step of forming a third impurity region having a concentration gradient of an impurity element that imparts p-type conductivity in a direction parallel to the substrate by doping the impurity element that imparts p-type conductivity into the island semiconductor layer that forms the p-channel TFT of the driver circuit through the taper portion of the gate electrode and through the gate insulating film, and of forming at the same time a fourth impurity region by doping an impurity element that imparts p-type conductivity, but not via the taper portion of the gate electrode;
a ninth step of forming a first interlayer insulating film made of an inorganic insulating material over the n-channel TFT of the driver circuit, the pixel TFT and the p-channel TFT;
a tenth step of forming a second interlayer insulating film made of an organic insulating material in contact with the first interlayer insulating film;
an eleventh step of forming a pixel electrode having a light reflective surface over the second interlayer insulating film to be connected to the pixel TFT via an opening provided in the first interlayer insulating film and in the second interlayer insulating film;
a twelfth step of forming on the other substrate at least a transparent conductive film; and
a thirteenth step of bonding the one substrate to the other substrate through at least one column-shape spacer formed overlapping the opening. Or, a step of forming a conductive metallic wiring to be connected to the pixel TFT via an opening provided in the first interlayer insulating film and the second interlayer insulating film, and a step of forming a pixel electrode made from a transparent conductive film on the second interlayer insulating film to be connected to the metallic wiring may be applied.